mapping("tstsvs", "ISUBVSsa Rn, Rn -> EQ"); mapping("tstsvc", "ISUBVCsa Rn, Rn -> EQ"); mapping_end(); ?> <?php page_section("shf_class", "Shift instructions"); ?> The shift instructions provide for logical shift left, logical shift right, arithmetic shift right and rotate right. Additionally a 33-bit rotation is supported, and this is performed if a ROR Rn, #0 instruction is issued. <?php encoding_start(4, "Mnemonic"); encoding("lsl", "00", "Rd,SHF,P = Op1 << Op2"); encoding("lsr", "01", "Rd,SHF,P = Op1 >> Op2"); encoding("asr", "10", "Rd,SHF,P = Op1 >>> Op2"); encoding("ror", "11", "Rd,SHF,P = Op1 >><< Op2 (immediate not zero)"); encoding("rrx", "11", "Rd,SHF,P = P,Op1 >><< (33)1 (immediate of zero)"); encoding_end(); ?> The native shift instruction is mapped to a shift instruction. If not extended then the conditional is derived in the standard way, and the registers are mapped in the standard way with the Rn specified in the instruction mapping both for Rn and Rd. If extended then the extended mappings are used. <p> <?php mapping_start("Native", "Internal"); mapping("lsl", "ILSLccs Rn, Rm -> Rd");
encoding("MVN", "0110", "MVN"); encoding("ANDC", "0111", "ANDC"); encoding("ANDX", "1000", "ANDX"); encoding("XORF", "1001", "XORF"); encoding("XORL", "1011", "XORL"); encoding("BITR", "1100", "BITR"); encoding("BYTR", "1101", "BYTR"); encoding_end(); ?> <?php page_section("shift_subclass", "Shift instruction subclasses"); ?> <?php encoding_start(4, "Subclass"); encoding("LSL", "0000", "LSL"); encoding("LSR", "0001", "LSR"); encoding("ASR", "0010", "ASR"); encoding("ROR", "0011", "ROR"); encoding("ROR33", "0100", "Rotate right 33-bit value (33rd bit comes from carry flag)"); encoding_end(); ?> <?php page_section("memory_subclass", "Memory (load/store) instruction subclasses"); ?> encoding_start( 4, "Subclass" ); encoding( "Preindex", "1xxx", "The transaction adds/subtracts the offset to the index and uses the result as the address" ); encoding( "Postindex", "0xxx", "The transaction adds/subtracts the offset to the index in the ALU but uses the 'Rn' value as the address" );