bit_breakout_bits_split("1100");
bit_breakout_bits(-1, "Rd <= number of ones in (Op1 & Op2)");
bit_breakout_hdr("xorlast");
bit_breakout_bits_split("1101");
bit_breakout_bits(-1, "Rd <= Op1 + Op2");
bit_breakout_hdr("bitreverse");
bit_breakout_bits_split("1110");
bit_breakout_bits(-1, "Rd <= Op2 (bottom byte bit reversed)");
bit_breakout_hdr("bytereverse");
bit_breakout_bits_split("1111");
bit_breakout_bits(-1, "Rd <= Op2 byte reversed");
bit_breakout_end();
?>
<?php
page_subsection("gp", "General purpose mode ALU instructions");
?>
This area is not yet cleaned up.
<?php
bit_breakout_start(4, "Mnemonic");
bit_breakout_hdr("xorfirst");
bit_breakout_bits_split("1000");
bit_breakout_bits(-1, "Number of first bit set in Op1 ^ Op2");
bit_breakout_hdr("rsb");
bit_breakout_bits_split("1001");
bit_breakout_bits(-1, "Rd <=-Op1 + Op2");
bit_breakout_hdr("bic");
bit_breakout_bits_split("1010");
bit_breakout_bits(-1, "Rd <= Op1 &~Op2");
</td>
</tr>
<tr>
<td>special_cp_trail_2</td>
<td>bit</td>
<td>
Asserted if any condition of 'cp' should use the AND of the old condition passed signal with the current condition passed signal; basically, this provides for some native GIP tricks. <br>
This is generally deasserted, and may not be used.
</td>
</tr>
</table>
<?php
page_subsection("outputs", "Outputs");
?>
<p>
The ALU stage will also generate outputs: again, 'ports' from the ALU stage
</p>
<table border=1>
<tr>
<th>Port</th>
<th>Type</th>
<th>Timing</th>
<th>Details</th>
</tr>
<tr>
<li>Shift the mutliplier right by two bits (logical, not arithmetic)</li>
<li>Shift the multiplicand left by two bits</li>
</ol>
The multiplication can be terminated when the multiplier is all zero and the
carry is zero, or when the multiplicand is zero.
<br>
Initialization requires the accumulator to be set to the value 'z' and the
multiplier and multiplicand to be stored in the correct places.
</p>
<?php
page_subsection("division", "Division");
?>
<p>
A divide instruction can be implemented with the divide step instruction, one
bit at a time. Say a calculation of the form r=x/y needs to be performed.
The basic divide step per bit can be performed as follows:
<ol>
<li>
Subtract B from ACC as the ALU result, generating the carry
</li>
<li>OR SHF with A as the logical result
</li>
<li>If B less than or equal to ACC (carry=1) then store the ALU result in ACC,
and the logical result in SHF</li>
arm_emulation_table_instruction("MOVS PC, #imm", "IMOVSAF #imm -> PC", "", "{$move_ops}<br>{$effects_acc_zn}<br>{$differs}");
arm_emulation_table_instruction("ADDS PC, Rn, #imm", "IADDSAF Rn, #imm -> PC", "", "{$repl_rn}<br>{$arith_ops}<br>{$effects_acc_zcvn}<br>{$differs}");
arm_emulation_table_instruction("BICS PC, Rn, #imm", "IBICSAF Rn, #imm -> PC", "", "{$repl_rn}<br>{$logic_ops}<br>{$effects_acc_zn}<br>{$differs}");
arm_emulation_table_instruction("ADDEQ Rd, Rn, #imm", "IADDEQ Rn, #imm -> Rd", $rd_not_pc, "{$repl_rn}<br>{$arith_logic_ops}<br>{$effects_nothing}<br>{$conds}");
arm_emulation_table_instruction("ADDEQ PC, Rn, #imm", "IADDEQF Rn, #imm -> PC", "", "{$repl_rn}<br>{$arith_logic_ops}<br>{$effects_nothing}<br>{$conds}");
arm_emulation_table_instruction("ADDEQS Rd, Rn, #imm", "IADDEQS Rn, #imm -> Rd", $rd_not_pc, "{$repl_rn}<br>{$arith_ops}<br>{$effects_acc_zcvn}<br>{$conds}");
arm_emulation_table_instruction("ADDEQS PC, Rn, #imm", "IADDEQSF Rn, #imm -> PC", "", "{$repl_rn}<br>{$arith_ops}<br>{$effects_acc_zcvn}<br>{$conds}<br>{$differs}");
arm_emulation_table_instruction("ADDEQ Rd, Rn, Rm", "IADDEQ Rn, Rm -> Rd", $rd_not_pc, "{$repl_rn_rm}<br>{$arith_logic_ops}<br>{$effects_nothing}<br>{$conds}");
arm_emulation_table_instruction("ADDEQ PC, Rn, Rm", "IADDEQF Rn, Rm -> PC", "", "{$repl_rn_rm}<br>{$arith_logic_ops}<br>{$effects_nothing}<br>{$conds}");
arm_emulation_table_instruction("ADDEQS Rd, Rn, Rm", "IADDEQS Rn, Rm -> Rd", $rd_not_pc, "{$repl_rn_rm}<br>{$arith_ops}<br>{$effects_acc_zcvn}<br>{$conds}");
arm_emulation_table_instruction("ADDEQS PC, Rn, Rm", "IADDEQSF Rn, Rm -> PC", "", "{$repl_rn_rm}<br>{$arith_ops}<br>{$effects_acc_zcvn}<br>{$conds}<br>{$differs}");
arm_emulation_table_end();
?>
<?php
page_subsection("shifted", "Shifted data processing instructions");
?>
<p>
Shifted data processing operations map to two internal instructions: a shift operation whose results
are placed in 'SHF' and 'P', and a following ALU operation utilizing that shift operation. The
second ALU operation is very similar to an unshifted data processing ARM instruction mapping, except 'Rm' is
replaced with 'SHF', and 'P' is appended to any instruction that includes the 'S' modifier.
</p>
<p>
ARM instructions with a shift are of the form: ADD Rd, Rn, Rm, LSL Rs or ADD Rd, Rn, Rm, LSL #5. The first
internal shift operation instruction implements the 'Rm LSL Rs' or 'Rm LSL #5' portion of the instructions.
</p>
<li>Get r1 to point to a struct pt_regs *. What is this?
<li>Handle the interrupt with asm_do_IRQ
<li>If the kernel is preemptible and preemption is needed here, then enable IRQs, schedule, and disable IRQs. Dont know how this works.
<li>Call ret_to_user, in entry-common.S, with 'why' of 0.
</ol>
</ol>
</p>
<?php
page_subsection("swi_code", "Linux ARM SWI code");
?>
<p>
A system call, i.e. a SWI, vectors through vector_swi, in entry-common.S. This code (obviously entered in SVC mode):
<ol>
<li>Save user registers
<ol>
<li>Save calling r0-r12 on SVC stack
<li>Save r13_usr, r14_usr on SVC stack
?>
The hardware interfaces into and out of the fabric are well defined,
with signals specified as early or late in the clock cycle. Early
signals are required to be generated from a register with up to 2
layers of simple (nand) logic on the output of the register. Late
signals may go through more logic, and are expected to go through at
most 2 layers of simple (nand) logic prior to the clock edge. Medium
arrival signals are expected to be driven by early arrival signals,
and may generate a late signal, using a small amount of propagation
time. For complex systems, though, propagation delays are expected to
be too large for medium signals to be used; only simple systems can
use medium signals.
<?php
page_subsection("into", "Signal definition for data in to fabric");
?>
<?php
signal_list("Ports on postbus source");
signal_output("Type", "2", "early", "Type of transaction word");
signal_output("Data", "32", "early", "Data for transaction word");
signal_input("Ack", "1", "late", "Acknowledge data presented in this cycle");
signal_end();
signal_list("Ports on postbus target");
signal_output("Ack", "1", "early", "Will take presented data");
signal_input("Type", "2", "late", "Type of transaction word");
signal_input("Data", "32", "late", "Data for transaction word");
signal_end();
signal_list("Ports on simple postbus router");
signal_input("n SrcType", "2*n", "medium", "Type of transaction word (one per source)");
function announces_listing($sess, $dopon, $select, $lres, $view_number, $page, $cs, $cs1, $uoz, $rub, $pri, $keyword, $age)
{
// dark row - name
?>
<col class="col_1">
<col class="col_2">
<col class="col_3">
<col class="col_4">
<col class="col_5">
<thead>
<tr class="th_main">
<th><?php
echo $lres;
?>
</td>
<th colspan="<?php
echo $cs1;
?>
"> </td>
</tr>
</thead>
<?php
$start = $page * $view_number;
//first announce for view
$sort = "ann_oq = '{$dopon}' and {$select}";
// mysql query
// query for announces
@($sqo = mysql_query("SELECT * FROM uniletim_announces WHERE {$sort} AND ul_group = '{$sess['4']}' ORDER BY ann_date DESC LIMIT {$start},{$view_number}")) or die($query_error);
if (mysql_num_rows($sqo) == 0) {
echo "<tr><td>" . _NO_ANNOUNCE . "</td></tr>\n";
} else {
$i = 0;
while ($roz = mysql_fetch_row($sqo)) {
if ($i % 2 == 0) {
$tb_class = '';
} else {
$tb_class = " class=tb_dark";
}
// announce content
?>
<tbody <?php
echo $tb_class;
?>
>
<tr class="tb_content" <?php
echo $bgcolor;
?>
>
<td colspan="<?php
echo $cs;
?>
">
<?php
echo $roz[7];
?>
</td>
</tr><?php
// announce info
?>
<tr class="tb_info"><?php
// author
if ($uoz == "") {
?>
<td>
<B><?php
echo _FROM;
?>
: </B><?php
if ($auth != "0") {
member_link($roz[1]);
} else {
member_name($roz[1]);
}
?>
</td><?php
}
?>
<td>
<?php
$timed = Date("d.m.Y", $roz[4]);
echo "{$timed}";
?>
</td><?php
// news
if ($dopon == "news") {
?>
<td> </td>
<td> </td> <?php
} else {
?>
<td> <?php
if ($pri == "") {
?>
<B><?php
echo _SUBSECTION;
?>
: </B><?php
page_subsection($roz[3], $auth, $sess);
}
?>
</td><?php
// timebank (no price)
if ($sess[3] == "timebank") {
?>
<td> </td><?php
// normal
} else {
?>
<td align="right">
<B><?php
echo _PRICE;
?>
: </B><?php
echo "{$roz['8']}";
?>
</td> <?php
}
}
// edit or delete announce
if ($uoz != "") {
if ($sess[5] >= "2" || $uoz == $sess[2]) {
?>
<td width="50" align=center<?php
echo $bgcolor;
?>
>
<A HREF="index.php?action=form&type=edit&eid=<?php
echo "{$roz['0']}";
?>
"><?php
echo _CHANGE;
?>
</A>
</td>
<td width="50" align=center<?php
echo $bgcolor;
?>
>
<A HREF="index.php?action=user&type=delete&did=<?php
echo "{$roz['0']}";
?>
" onclick="return confirm('<?php
echo _RLY_DLT_ANNO;
?>
')"><?php
echo _DELETE;
?>
</A>
</b></td><?php
}
}
?>
</tr>
</tbody>
<?php
if ($i == 10) {
break;
}
$i++;
}
}
?>
<tfoot>
<tr class="th_sub">
<th><?php
if ($sess[5] >= "2" & $usoz != "") {
?>
<a HREF="index.php?action=form&type=new&dp=<?php
echo "{$dopon}";
?>
&rub=<?php
echo "{$rub}";
?>
&pri=<?php
echo "{$pri}";
?>
&a_id=<?php
echo "{$uoz}";
?>
"><?php
echo _INSERT;
?>
</A><?php
} else {
?>
<a HREF="index.php?action=form&type=new&dp=<?php
echo "{$dopon}";
?>
&rub=<?php
echo "{$rub}";
?>
&pri=<?php
echo "{$pri}";
?>
"><?php
echo _INSERT;
?>
</A><?php
}
?>
</th>
<th colspan="<?php
echo $cs1;
?>
"align="right">
<?php
// paging of extracts
$id = "ann_id";
$table = "uniletim_announces";
if (isset($uoz)) {
$link = "index.php?action=user&uoz={$uoz}&page=";
} elseif (isset($pri)) {
$link = "index.php?rub={$rub}&pri={$pri}&page=";
} else {
$link = "index.php?rub={$rub}&keyword={$keyword}&age={$age}&page=";
}
page_counter($id, $table, $sort, $view_number, $sess, $link, $i, $page);
?>
|
</th>
</tr>
</tfoot>
<?php
}
does not contain a useful register, otherwise it contains the register number that the accumulator holds. This value
is updated every time an instruction is inserted into the pipeline. If an instruction requires a register
whose value is in the accumulator (i.e. if the register number matches the 4-bit value) then the accumulator can be
used as the source of the value instead of the register number itself. Note that the key word is 'can', and not shall. Some
instructions do not use the accumulator as a source; this simplifies the logic and reduces corner cases.
<br>
Note that the concept of the accumulator 'holding' a value is not effected by the pipeline; the emulation
hardware ignores the pipeline entirely, and just feeds instructions in at the start of the pipeline, so
'holds' relates to what the accumulator will hold when the instruction just being placed into the pipeline actually is
executed. So, following the insertion of an 'IADDA' instruction into the accumulator will be though to hold
the result of the addition, even though the actual instruction is executed some cycles later.
<?php
page_subsection("setting", "Setting the accumulator");
?>
The accumulator can only be set by ALU instructions; that is its function. Mirroring this, it is explicitly set
(for ALU forwarding) only by ARM data processing instructions that have a result (i.e. ADD, ADC, SUB, SBC, RSB, RSC, AND, ORR, XOR, BIC, MOV, MVN).
A conditional instruction, as it may or may not be executed, <em>does not</em> set the accumulator.
Any internal instruction that is inserted into the pipeline that does set the accumulator from a data processing instruction
marks the accumulator as valid containing the target register. Any other internal instruction that is inserted into the
pipeline marks the accumulator as invalid.
<p>
<?php
page_ep();
include "{$toplevel}web_assist/web_footer.php";
?>